While the present invention is not limited to field effect transistors, and may find application in bipolar, CMOS, or other semiconductor technology, reference will be made to field effect transistors, often referred to as MOS transistors. Fundamentally, MOS transistors generally include highly doped regions called sources and drains in a semiconductor surface, having a gate region or channel between the source and drain regions. A gate electrode is located above and electrically biased to form or eliminate the channel. MOS transistors are separated from nearby transistors or other devices by an isolation technique. Two prevalent techniques are the use of a thick field oxide or a field shield. The field shield approach is disclosed, for example, in U.S. Pat. No. 4,570,331, entitled "Thick Oxide Field-Shield CMOS Process," issued on Feb. 18, 1986 to Inmos Corporation upon the application of S. Sheffield Eaton and Cheng-Cheng Hu.
In addition to isolating the transistor, for there to be utility, connections must be made to the source, drain and gate of the transistor. MOS transistors used in integrated circuits generally include a thick interlevel dielectric which is added on top of the transistor structure. After the dielectric is in place, at some time contact windows are etched to allow contacts to be made to the transistor source, drain and gate. When very small geometries are used, the contact window tends to have an "aspect ratio" (height divided by base) that becomes too large (i.e. greater than 0.5), resulting in poor step coverage by a sputtered or evaporated conductor. The narrow "base" dimension (such as the width of a source/drain region) is small because of the small geometries, though the thickness of interlevel dielectric remains relatively large. In consequence, a main object of the present invention is to provide a structure and process which protects elements of the transistor from such dangers of etching and simultaneously allows larger windows to be constructed even in small geometries.
It will be understood that the preferred form of the invention involves the use of a titanium nitride (TiN) layer covering a titanium silicide (TiS.sub.2) region that is found in the contact area. This part of the combination is known to the semiconductor industry, and reference may be had to Stevens, McClure and Hill, U.S. Pat. No. 4,784,973 issued on Nov. 15, 1988 to INMOS Corporation, entitled "Semiconductor Contact Silicide/Nitride Process with Control for Silicide Thickness." That patent explains also that titanium nitride can be used as a metallurgic barrier against reactions between a silicon substrate and an aluminum contact material to a source or drain, for example. The '973 patent discloses a process using a control layer located in the contact opening and formed illustratively of a compound of silicon, oxygen and nitrogen, or silicon oxide. A layer of titanium is added, and titanium silicide is formed under the control layer, and titanium nitride is formed above the control layer. It may also be noted, however, that the titanium is added after a relatively thick layer of dielectric such as BPSG is established.
By way of further background, an application of the combination of titanium nitride with titanium silicide is discussed by Tang, Wei, Haken, Holloway, Wan and Douglas in "VLSI Local Interconnect Level Using Titanium Nitride," International Electron Devices Meeting 1985 (IEDM 85), pp. 590-93. Tang et al. use the titanium nitride for local interconnects.
The present invention has further aspects, however, than merely locating a titanium nitride layer over the contact area. These further aspects are discussed infra.